Sundance SMT391-VP - Manual (Page 34)

Version 1.3 Page 34 of 41 SMT391-VP User Manual
First off the LE line is pulled low and then the MSB of data is loaded onto the Data
line. The Clock line is then driven high and low and a new Data line value is clocked
into the Pll on each rising edge of the Clock line. The Data line is driven with the
registers setup and the Clock line driven high and low until the Data line has reached
the LSB. To end the sequence the LE line is pulled high.
There are two ways to operate the LE line as also shown in the figure below. The
figure also explains how to configure the device.
Figure 22 – PLL Configuration Sequence.
The figure below explains the state diagram residing in the firmware design
(SMT338-VP’s Fpga). This design ultimately executes the procedures explained in
the previous figures and paragraph.