Sundance SMT391-VP - Manual (Page 12)

Version 1.3 Page 12 of 41 SMT391-VP User Manual
- CLKI
Æ
ADCQ
Any other configuration isn’t supported by the SMT391-VP. For example the
interlacing mode of the ADC is not supported by the default firmware of the
SMT391-VP.
The SMT391 block also includes the 3-wires interface used to configure the ADC as
well as the interfaces used to configure the clocks of the SMT391 daughter module.
Refer to the SMT391 user manual for more information about the clocks generation
feature of the SMT391-VP module.
ADC data interface
Support for a sub-set of the command controllable features of the Atmel ADC is
implemented in the firmware of the SMT391-VP. The ADC should be configured as
follow:
• Data Demux 1:2 mode
• Output Clock Fs/4
ADC 3-wire interface
The settings stored in the register block of the SMT391-VP are sent to the ADC via
this interface.
Refer to the appendix for more information about this interface.
PLL - VCO (LMX2330U) interface
A three wire uni-directional control interface is implemented between the FPGA and
the PLL on the daughter card. This PLL sets and controls the voltage for the VCO
that generates the main clock.
Refer to the LMX2330U user guide for the detailed description of the PLL.
Clock synthesiser (SY89430) interface
A three wire uni-directional controls interface is implemented between the FPGA and
the Micrel clock synthesizer on the daughter card. The clock synthesizer can
generate a variable 50 – 950 MHz clock. The jitter on this clock is higher than on the
main PLL+VCO clock, but it is convenient for testing.
External clocks
The external clocks are not supported by the SMT391-VP.
Triggers
There are two main sources for the trigger. The first is an LVPECL trigger received
over the MMBX connector. The second is a trigger command. The trigger command
is received over the Comport interface.