Sundance SMT391-VP - Manual (Page 38)

Version 1.3 Page 38 of 41 SMT391-VP User Manual
Figure 28 – Timing Diagram for the Atmel ADC.
Sdata gets clocked into the ADC on the rising edges of Sclk. For the initialisation of
the sequence Sldn must be pulled high for one clock and then low again after the one
clock. This will initialize the start condition for the ADC to be configured and then the
data bits are clocked into it MSB first.
The state machine that clocks these bits into the ADC is shown in the figure below.
This state machine is implemented in the firmware of the SMT338-VP FPGA.
Figure 29 – State Machine Driving the ADC Serial Interface.