Measurement Computing PCI-DAS6071 - Manual (Page 47)

PCI-DAS6071 User's Guide Specifications
47
Table 30. 64-channel single-ended mode pinout
Pin Signal Name Pin Signal Name
1 LLGND 51 LLGND
2 CH0 IN 52 CH16 IN
3 CH32 IN 53 CH48 IN
4 CH1 IN 54 CH17 IN
5 CH33 IN 55 CH49 IN
6 CH2 IN 56 CH18 IN
7 CH34 IN 57 CH50 IN
8 CH3 IN 58 CH19 IN
9 CH35 IN 59 CH51 IN
10 CH4 IN 60 CH20 IN
11 CH36 IN 61 CH52 IN
12 CH5 IN 62 CH21 IN
13 CH37 IN 63 CH53 IN
14 CH6 IN 64 CH22 IN
15 CH38 IN 65 CH54 IN
16 CH7 IN 66 CH23 IN
17 CH39 IN 67 CH55 IN
18 LLGND 68 LLGND
19 CH8 IN 69 CH24 IN
20 CH40 IN 70 CH56 IN
21 CH9 IN 71 CH25 IN
22 CH41 IN 72 CH57 IN
23 CH10 IN 73 CH26 IN
24 CH42 IN 74 CH58 IN
25 CH11 IN 75 CH27 IN
26 CH43 IN 76 CH59 IN
27 CH12 IN 77 CH28 IN
28 CH44 IN 78 CH60 IN
29 CH13 IN 79 CH29 IN
30 CH45 IN 80 CH61 IN
31 CH14 IN 81 CH30 IN
32 CH46 IN 82 CH62 IN
33 CH15 IN 83 CH31 IN
34 CH47 IN 84 CH63 IN
35 AISENSE 85 DIO0
36 D/A OUT 0 86 DIO1
37 D/A GND 87 DIO2
38 D/A OUT1 88 DIO3
39 PC +5 V 89 DIO4
40 AUXOUT0 / D/A PACER OUT 90 DIO5
41 AUXOUT1 / A/D PACER OUT 91 DIO6
42 AUXOUT2 / SCANCLK 92 DIO7
43 AUXIN0 / A/D CONVERT / ATRIG 93 CTR1 CLK
44 D/A EXTREF 94 CTR1 GATE
45 AUXIN1 / A/D START TRIGGER 95 CTR1 OUT
46 AUXIN2 / A/D STOP TRIGGER 96 GND
47 AUXIN3 / D/A UPDATE 97 CTR2 CLK
48 AUXIN4 / D/A START TRIGGER 98 CTR2 GATE
49 AUXIN5 / A/D PACER GATE 99 CTR2 OUT
50 GND 100 GND