2 processor, Table 4-1, Tunnel creek processor features – Artesyn NITX-315/NITX-315-ET Installation and Use (August 2014) User Manual
Page 58: Functional description

Functional Description
NITX-315/NITX-315-ET Installation and Use (6806800L71D)
58
4.2
Processor
NITX-315/NITX-315-ET is designed to support the Tunnel Creek processor. The features are
detailed in the table below:
Table 4-1 Tunnel Creek Processor Features
Feature
Description
Low-Power Intel Architecture Core
600 MHz (Ultra Low Power SKU), 1.0 GHz (Mainstream SKU) and 1.3
GHz(Premium SKU) with related TDP 2.7, 3.1, 3.3 W
System Memory Controller
Single-channel DDR2 memory controller 32-bit data bus Supports
DDR2 800 MT/s data rates.
Supports only soldered-down DRAM configurations.
The memory controller does not support SODIMM or any type of
DIMMs currently.
Video Decode
supports MPEG2, MPEG4, VC1, WMV9, H.264 (main, baseline@L3
and high-profile level 4.0/4.1), and DivX.
Video Encode
supports MPEG4, H.263, H.264 (baseline@L3), and VGA/QGA.
Display Interfaces
supports LVDS and Serial DVO display ports permitting simultaneous
independent operation of two displays
The LVDS interface supports pixel color depths of 18 and 24 bits with
maximum resolution up to 1280x768 @ 60Hz.
The Serial DVO (SDVO) Display Interface can provide maximum
resolution up to 1280x1024 @ 85Hz.
PCI Express
has four x1 lane PCI Express root ports supporting the PCI Express
Base Specification, Revision 1.0a.
LPC Interface
The Tunnel Creek Processor implements an LPC interface as
described in the LPC1.1 Specification.
Intel High Definition Audio (Intel HD
Audio) Controller
The Intel HD Audio controller supports up to four audio streams, two
in and two out. With the support of multi-channel audio stream, 32-
bit sample depth, and sample rate up to 192 kHz.
SMBus Host Controller
The Tunnel Creek Processor contains an SMBus host interface that
allows the processor to communicate with SMBus slaves. This
interface is compatible with most I2C devices. The SMBus host
controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves).
See the System Management Bus (SMBus) Specification, Version 1.0.