Altera Transceiver Signal Integrity Development Kit, Stratix IV GX Edition User Manual
Page 7
Chapter 1: Overview
1–3
General Description
November 2011
Altera Corporation
Transceiver Signal Integrity Development Kit,
Stratix IV GX Edition Reference Manual
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General User Input/Output
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Eight-position user DIP switch
■
Six user push buttons
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Four directional LCD menu push buttons
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Hex rotary switch
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Eight user LEDs
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16 character × 2 line LCD
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Components and Interfaces
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10/100/1000 Ethernet PHY and RJ-45 Jack
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Transceiver Channels
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Six full-duplex transceiver channels from the same transceiver block
brought out to SMA connectors using stripline routing
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One full-duplex transceiver channel brought out to SMA connectors using
microstrip routing
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One channel brought out to SMAs with microstrip routing with 33 in. board
trace length on transmit and 7 in. board trace length on receive to simulate
the degradation associated with backplanes or long traces
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Power
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14-V – 20-V DC input
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2.5-mm Barrel Jack for DC power input
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On/Off slide power switch
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On-Board power measurement circuitry
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Heat Sink and Fan
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40-mm heat sink and 5-V DC fan combo
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)