Altera Transceiver Signal Integrity Development Kit, Stratix IV GX Edition User Manual
Page 38
2–28
Chapter 2: Board Components
Power
Transceiver Signal Integrity Development Kit,
November 2011
Altera Corporation
Stratix IV GX Edition Reference Manual
J9
F6
Banana jack and fuse
for supplying external
power to VCCH
Johnson
Components
111-0702-001
Littelfuse Inc.
154 005.DR
J10
F7
Banana jack and fuse
for supplying external
power to VCCL
Johnson
Components
111-0702-001
Littelfuse Inc.
154 002
J7
F84
Banana jack and fuse
for supplying external
power to VCCR and
VCCT
Johnson
Components
111-0702-001
Littelfuse Inc.
154 002
J4, J5
—
Banana jack
connected to board
GND
Johnson
Components
111-0703-001
Littelfuse Inc.
—
Note to
:
(1) The banana jacks and fuses whose component reference on the engineering silicon board differ from the production silicon board are listed in
Table 2–31. Banana Jack and Fuses Component Reference (Part 2 of 2)
(1)
Banana Jack
Board
Reference
Fuse Board
Reference
Device Description
Manufacturer
Manufacturer
Part Number
Manufacturer
Website
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)