Altera Transceiver Signal Integrity Development Kit, Stratix IV GX Edition - Manual (Page 33)

Chapter 2: Board Components 2–23
Components and Interfaces
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GX Edition Reference Manual
Table 2–23 lists the SPI Bus pin connections to the FPGA for the power measurement
circuitry.
Table 2–24 lists the ADC component reference and manufacturing information.
Ethernet Port
The Stratix IV GX transceiver signal integrity development board incorporates a triple
speed 10/100/1000 Base-T Ethernet port. The implementation uses a discrete Ethernet
PHY device and RJ45 connector with integrated magnetics connected to the FPGA.
Figure 2–9 shows the block diagram of the Ethernet port.
Table 2–25 lists the components used for the Ethernet port and the manufacturing
information.
Table 2–23. Power Measurement Pin-Out
Board Reference Description
Schematic Signal
Name
I/O Standard
Stratix IV GX
Device Pin
Number
Other
Connections
U14 pin 17 Serial Data Out S4_SPI_MISO
2.5-V CMOS
U33 pin C11 —
U14 pin 20 Serial Data In S4_SPI_MOSI U33 pin B11 —
U14 pin 18 Serial Clock S4_SPI_SCK U33 pin C12 —
U14 pin 16 Chip Select S4_ADC_CSn U33 pin C13
10-k Ω pull-up
resistor to 2.5 V
U14 pin 19 Frequency Control S4_ADC_Fo U33 pin A13 —
Table 2–24. ADC Component Reference
Board Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U14 8-Channel differential 24-bit ADC Linear Technology LTC2418CGN#PBF www.linear.com
Figure 2–9. Ethernet Port
Stratix IV GX
FPGA
(U33)
SGMII/RGMII Marvell 88E1111
(U40)
TX/RX
RJ45 +
Mangetics (J68)
Table 2–25. Ethernet Component References
Board
Reference
Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U40 10/100/1000 Base-T Ethernet PHY
Marvell
Semiconductor
88E1111-B2-CAA1C000 www.marvell.com
J68 RJ45 with integrated magnetics Halo Electronics HFJ11-1G02ERL www.haloelectronics.com