Power distribution system, Power distribution system –26 – Altera Transceiver Signal Integrity Development Kit, Stratix IV GX Edition User Manual
Page 36
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2–26
Chapter 2: Board Components
Power
Transceiver Signal Integrity Development Kit,
November 2011
Altera Corporation
Stratix IV GX Edition Reference Manual
Power Distribution System
shows the power distribution system on the board.
Figure 2–10. Power Distribution System
Switching
Regulator
14 V - 20 V
DC Input
(60 W )
max
U1
LTM4601
LTM4601
Switching
Regulator
U2
0.9 V @ 24 A
VCC
VCCHIP
5 V @ 12 A
LTM4601
Switching
Regulator
U3
3.3 V @ 8 A
VCCD_PLL
Bead
2.5 V @ 8 A
3.3 V Devices
LTM4616
Dual Output
Micromodule
U5
LEGEND
Stratix IV GX Power
Other Power
VCCIO
VCCPD
VCCREF
VCCPGM
VCCBAT
VCC_CLKIN
2.5 V Devices
Bead
LT3080-1
LDO
2.5 V / 3.0 V
@ 1.1 A
U4
LT1761
LDO
U37
VCCA
1.8 V
@ 0.1 A
3.3V_Analog
ADC
LCD, Fan,
Pat Board
VCCA_PLL
VCCAUX
VCCL_GXB
1.1 V
@ 0.5 A
LTC3025-1
LDO
(U11)
LT3080-1
LDO
1.4 V / 1.5 V
@ 2.2 A
LTC3025-1
LDO
1.5 V
@ 0.5 A
(U10, U12)
VCCH_GXB
VCCIO_1.5 V
VCCPT
(U13)
LT3080-1
LDO
1.1 V
@ 4.4 A
VCCRT
LT3080-1
LDO
LTC3025-1
LDO
(U6, U9)
1.2 V
@ 1.1 A
(U25)
1.8 V
@ 0.5 A
(U38)
VCC_1.2V
Ethernet
VCC_1.8V
Flash
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)