Jtag interface, Jtag interface -28, Figure 2–8. example mezzanine cards – Altera Arria GX Development Board User Manual
Page 38
2–28
Reference Manual
Altera Corporation
Arria GX Development Board
October 2007
Standard Communication Ports
Figure 2–8. Example Mezzanine Cards
JTAG Interface
The board provides a right-angle, 10-pin JTAG header. The JTAG header
protrudes through the front panel of the PCIe card, which positions it well
for internal accessibility while the box is closed. Pin 1 is located on the
side nearest the SFP connectors.
The JTAG header can be used for JTAG-based FPGA programming as
well as communication to a standard computer using a USB-Blaster
download cable. The default USB-Blaster driver that Quartus II software
installs for JTAG programming and SignalTap debugging.
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For more information on the JTAG chain, refer to
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- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
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- ALTDQ_DQS IP (117 pages)
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