Altera Arria GX Development Board - Manual (Page 16)

2–6 Reference Manual Altera Corporation
Arria GX Development Board October 2007
Configuration Schemes
Figure 2–3. Arria GX Device Clocking Resources
Configuration
Schemes The Arria GX device is configured using the on-board MAX II complex
programmable logic device (CPLD) and a 16-bit page-mode flash
memory device.
The 512 Mb flash memory device can hold eight designs, where each
design is 16,951,824 bits in size for the EP1AGX60DF780 device plus
32 MBytes for other storage.
This section discusses:
■ JTAG chain configuration
■ Flash memory configuration
■ MAX II configuration controller
■ Configuration push button
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