Development board block diagram, Handling the board – Altera DSP Development Kit, Stratix V Edition User Manual
Page 8
1–4
Chapter 1: Overview
Development Board Block Diagram
DSP Development Kit, Stratix V Edition
July 2012
Altera Corporation
Reference Manual
Development Board Block Diagram
shows the block diagram of the DSP Development Kit, Stratix V Edition.
Handling the Board
When handling the board, it is important to observe the following static discharge
precaution:
c
Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
Figure 1–1. DSP Development Kit, Stratix V Edition Block Diagram
Port A
Port B
1152 MB
DDR3
4.5 MB
QDRII+ SRAM
Push Buttons
and Switches
LED
CPLD
64 MB
Flash
64 MB
Flash
x8 Edge
Programmable
Oscillators
50 MHz, 100 MHz,
148 MHz, 156 MHz
QSFP
REFCLK
SMA IN
GigE
PHY
SDI
TX/TX
On-Board
USB- Blaster II
and USB Interface
x4 XCVR
x1 (LVPECL)
x1
x1 XCVR
x72
x18
72 MB CIO
RLDRAM II
x18
EPCQ
x4
x4
x8
x16
x4
XCVR x8
x32 Config
x32
x80
CLKIN x3
CLKOUT x3
XCVR x8
x80
CLKIN x3
CLKOUT x3
XCVR x6
ADDR
JTAG Chain
5SGSMD5K2F40C2N
Micro-USB
2.0
x19 USB Interface
LVDS/Single-Ended
DQS/Single-Ended
x16
x16
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)