Program select push button, Cpu reset push button – Altera DSP Development Kit, Stratix V Edition User Manual

Page 30

2–22

Chapter 2: Board Components

Configuration, Status, and Setup Elements

DSP Development Kit, Stratix V Edition

July 2012

Altera Corporation

Reference Manual

Program Select Push Button

The program select push button, PGM_SEL, is an input to the MAX V CPLD System
Controller. The push button toggles the PGM_LED[2:0]setting that selects which
location in the flash memory is used to configure the FPGA. Refer to

Table 2–9

for the

configuration settings.

Table 2–20

lists the program select push button component reference and

manufacturing information.

CPU Reset Push Button

The CPU reset push button, CPU_RESETn, is an input to the Stratix V GS DEV_CLRn pin
and is an open-drain I/O from the MAX V CPLD System Controller. This push button
is the default logic reset for the FPGA logic. The MAX V System Controller also
drives this push button during POR.

You must enable the CPU_RESETn signal within the Quartus II software for this reset
function to work. Otherwise, the CPU_RESETn acts as a regular I/O pin. When you
enable the signal in the Quartus II software, and then pulled high on the board, this
push button resets every register within the FPGA with a low signal.

Table 2–21

lists the CPU reset push button component reference and manufacturing

information.

Table 2–20. Program Select Push Button Component Reference and Manufacturing Information

Board

Reference

Description

Manufacturer

Part Number

Manufacturer Website

Push button

Dawning Precision Co., Ltd.

TS-A02SA-2-S100

www.dawning2.com.tw

Table 2–21. CPU Reset Configuration Push Button Component Reference and Manufacturing Information