Altera DSP Development Kit, Stratix V Edition - Manual (Page 41)

Chapter 2: Board Components 2–33
Components and Interfaces
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
A16 PCIE_TX_P0 1.4-V PCML AU36 Transmit bus
A17 PCIE_TX_N0 1.4-V PCML AU37 Transmit bus
A21 PCIE_TX_P1 1.4-V PCML AR36 Transmit bus
A22 PCIE_TX_N1 1.4-V PCML AR37 Transmit bus
A25 PCIE_TX_P2 1.4-V PCML AN36 Transmit bus
A26 PCIE_TX_N2 1.4-V PCML AN37 Transmit bus
A29 PCIE_TX_P3 1.4-V PCML AL36 Transmit bus
A30 PCIE_TX_N3 1.4-V PCML AL37 Transmit bus
A35 PCIE_TX_P4 1.4-V PCML AG36 Transmit bus
A36 PCIE_TX_N4 1.4-V PCML AG37 Transmit bus
A39 PCIE_TX_P5 1.4-V PCML AE36 Transmit bus
A40 PCIE_TX_N5 1.4-V PCML AE37 Transmit bus
A43 PCIE_TX_P6 1.4-V PCML AC36 Transmit bus
A44 PCIE_TX_N6 1.4-V PCML AC37 Transmit bus
A47 PCIE_TX_P7 1.4-V PCML AA36 Transmit bus
A48 PCIE_TX_N7 1.4-V PCML AA37 Transmit bus
A5 PCIE_JTAG_TCK 1.4-V PCML — JTAG chain clock
A6 PCIE_JTAG_TDI 1.4-V PCML — JTAG chain data in
A7 PCIE_JTAG_TDO 1.4-V PCML — JTAG chain data out
A8 PCIE_JTAG_TMS 1.4-V PCML — JTAG chain mode select
A1 PCIE_PRSNT1N LVTTL — Presence detect DIP switch
B17 PCIE_PRSNT2N_X1 LVTTL — Presence detect DIP switch
B31 PCIE_PRSNT2N_X4 LVTTL — Presence detect DIP switch
B48 PCIE_PRSNT2N_X8 LVTTL — Presence detect DIP switch
A14 PCIE_REFCLK_N HCSL AF35 Motherboard reference clock
A13 PCIE_REFCLK_P HCSL AF34 Motherboard reference clock
B5 PCIE_SMBCLK LVTTL AN33 SMB clock
B6 PCIE_SMBDAT LVTTL AL34 SMB data
B11 PCIE_WAKEN_R LVTTL AN32 Wake signal
A11 PCIE_PERSTN LVTTL AC28 Reset
Table 2–37. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board
Reference
(J18)
Schematic Signal
Name
I/O Standard
Stratix V GS Device
Pin Number
Description