Altera DSP Development Kit, Stratix V Edition - Manual (Page 13)

Chapter 2: Board Components 2–5
Featured Device: Stratix V GS
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
Featured Device: Stratix V GS
The Stratix V GS development board features the Stratix V GS 5SGSMD5K2F40C2N
device (U15) in a 1517-pin FineLine BGA package.
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For more information about the Stratix V device family, refer to the Stratix V Device
Handbook .
Table 2–2 describes the features of the Stratix V GS 5SGSMD5K2F40C2N device.
Table 2–3 lists the Stratix V GS component reference and manufacturing information.
I/O Resources
Table 2–4 lists the Stratix V GS device pin count and usage by function on the
development board.
Power Supply
J18 PCI Express edge connector
Interfaces to a PCI Express root port such as an appropriate PC
motherboard.
J4 DC input jack Accepts a 19-V DC power supply.
SW2 Power switch
Switch to power on or off the board when power is supplied from the
DC input jack.
Table 2–1. DSP Development Kit, Stratix V Edition Components (Part 4 of 4)
Board Reference Type Description
Table 2–2. Stratix V GS 5SGSMD5K2F40C2N Features
ALMs
Equivalent
LEs
Registers
M20K
Blocks
MLAB
Blocks (Mb)
18-bit × 18-bit
Multipliers
PLLs
Transceiver
Channels
(14.1 Gbps)
Package Type
172,600 457,000 690,400 2,014 5.27 3,180 24 36
1517-pin
FineLine BGA
Table 2–3. Stratix V GS Component Reference and Manufacturing Information
Board
Reference
Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U15
FPGA, Stratix V GS F1517, 457K
LEs, leadfree
Altera Corporation 5SGSMD5K2F40C2NC2N www.altera.com
Table 2–4. Stratix V GS Pin Count and Usage (Part 1 of 2)
Function I/O Standard I/O Count Special Pins
DDR3 1.5-V SSTL 126 1 Diff ×9DQS
RLDRAM II 1.8-V SSTL 57 1 Diff ×3 DQS
QDRII+ SRAM 1.8-V HSTL 67 1 Diff ×2 DQS
MAX V System Controller 1.5-V CMOS 8 —
Flash 1.8-V CMOS 68 —
PCI Express ×8 2.5-V CMOS + XCVR 43 1 REFCLK