Altera HyperTransport MegaCore Function - Manual (Page 71)

© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
B. Stratix Device Pin Assignments
Introduction
This section provides general guidelines on how to assign the HyperTransport pins
for Stratix devices. Many rules differ based on the device and package you use, and
not all variations are documented here.
c You must compile your pin assignments in the Quartus II software version 9.1 or later
to verify they are correct before you commit the pin assignments to the board layout.
You should make sure the pin assignments will also work for any device you may
migrate to later, or any clock option you may consider using in the future.
The I/O pins that support the HyperTransport differential I/O standard are on the
sides of Stratix devices, specifically, I/O banks B1, B2, B5, and B6.
Guidelines
The general guidelines for HyperTransport I/O pin assignments are described below:
■ If your design uses a 400-MHz HyperTransport link clock, RxClk_i should use
one of these PLL clock input pin pairs that support the highest input clock rates:
■ CLK0p / CLK0n - Fast PLL1 - I/O Bank B2
■ CLK2p / CLK2n - Fast PLL2 - I/O Bank B1
■ CLK9p / CLK9n - Fast PLL3 - I/O Bank B6
■ CLK11p / CLK11n - Fast PLL4 - I/O Bank B5
If the CLK1 , CLK3 , CLK8 , and CLK10 inputs are used and drive the same respective
PLLs, the HyperTransport link frequency is limited to 300 MHz.
f
See the DC & Switching Characteristics chapter of the Stratix Device Handbook for the
most up to date information about the maximum input clock rates.
■ All of the I/O pins for the receive interface ( RxCAD_i[7:0] , RxCTL_i , and
RxClk_i ) must be in the same I/O bank, so that the high-speed de-serialization
circuitry can be connected to the same fast PLL.
■ All of the I/O pins for the transmit interface ( TxCAD_o[7:0] , TxCTL_o , and
TxClk_o ) must be in the same I/O bank, so that the high-speed serialization
circuitry can be connected to the same fast PLL.
■ If you are using the Shared Rx/Tx/Ref Clock option or the Shared Rx/Tx Clock
option, all of the transmit and receive interface pins must be in the same I/O bank,
because they all share a single fast PLL.