Altera HyperTransport MegaCore Function User Manual

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3–24

Chapter 3: Specifications

HyperTransport MegaCore Function Specification

HyperTransport MegaCore Function User Guide

Altera Corporation

Preliminary

Tx Buffer Ordering

Packets in the Tx buffers are transmitted in the same order they are written to the
different buffers. For example, the response buffer transmits all packets in the order
they are written into it. This implementation satisfies all ordering rule requirements in
the HT specification except for response and non-posted packets that have the

PassPW

bit cleared. If a response or non-posted packet has the

PassPW

bit cleared, the

HT specification requires that the response or non-posted packet must not be
transmitted before the preceding posted packet.

DatEna_i

Input

Data transfer enable. This signal functions as the

ena

signal in the Atlantic interface

specification with the HyperTransport MegaCore function as a slave sink.

DatEna_i

driven by the interface master and used to control the flow of data across the interface.

DatEna_i

behaves as a write enable.

Dav_o

Output

Data buffer is available. This signal functions as

dav

in the Atlantic interface. When

Dav_o

is high, it indicates that the buffer has sufficient storage for at least one complete packet
including command and data.

If there is room for at least two complete, full-size packets (9 64-bit words per packet)
when a start of packet is written,

Dav_o

remains asserted during the packet so that

another packet can be written immediately after the first. However, if there is only room for
one full-size packet,

Dav_o

is deasserted after the start of the packet is written and

reasserted again when the buffer has the room for at least one additional full-size packet.

The local-side application must sample

Dav_o

asserted to write the start of the packet, but

it should ignore

Dav_o

to write the subsequent words of the packet.

When a single word packet (i.e. with

Sop_i

and

Eop_i

asserted in the same cycle) is

written, it is typically not possible to start another packet in the following cycle. If there is
initially only room for one additional packet, then

Dav_o

is deasserted in the cycle

following the single word packet making it illegal to start writing a packet in that cycle.
Typically the user application must write the single word packet in cycle one, sample

Dav_o

in cycle two and if

Dav_o

is still asserted, start writing a new packet in cycle 3.

Special note for

TxRDav_o

only: Because the Tx response buffer also handles responses

generated internally in the HyperTransport MegaCore function by the CSR and end-chain
modules, the

TxRDav_o

signal can be deasserted at any time due to the internal usage. By

default, the HyperTransport MegaCore function accepts response packets written by the
user interface for one cycle after

TxRDav_o

is deasserted. If the local-side application

requires multiple clock cycles between sampling

TxRDav_o

asserted and writing the start

of packet (for example, due to a complex state machine or data pipeline), the window for
accepting packets can be increased by changing the

TxRDavToSopDelay

configuration

parameter.

TxPDav_o

and

TxNpDav_o

are only deasserted in response to user-written packets or

reset.

Table 3–7. Tx Command/Data Buffer Interface Signals (Part 2 of 2)

Signal Name

Direction

Description