Altera HyperTransport MegaCore Function - Manual (Page 57)

Chapter 3: Specifications 3–31
HyperTransport MegaCore Function Specification
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
Buffer Overflow Indicator Signals
Table 3–11 describes the buffer overflow indicator signals. When an a Rx buffer
overflows due to a failure in the HyperTransport link flow control mechanism, the
overflow error bit is set in the CSR HT capability link error 0 register. These signals
indicate which virtual channel buffer had the overflow. These signals are most useful
in simulation and typically do not need to be connected in the user design.
CSR Module
The CSR module contains all of the configuration space registers and handles write
requests, read requests and response accesses to the CSR space.
Table 3–12 and
Table 3–13 show the full CSR register map. Table 3–13 shows the primary interface
capabilities block format.
Table 3–11. Buffer Overflow Indicator Signals
Signal Name Direction Description
ClmdRCmdBufOvrFlw_Err_o Output Rx Response Command/Data buffer overflow.
ClmdPCmdBufOvrFlw_Err_o Output Rx Posted Command/Data buffer overflow.
ClmdNpCmdBufOvrFlw_Err_o Output Rx Non-Posted Command/Data buffer overflow.
Table 3–12. CSR Register Map Without Primary Interface Capabilities Block
Hyper Transport Technology Device Header
Address Byte 3 Byte 2 Byte1 Byte 0
00 Device ID (3) Vendor ID (3)
04 Status (4) Command (4)
08 Class Code (3) Revision ID (3)
0C BIST (1) Header Type (3) Latency Timer (1) Cache Line (1)
10 BAR0 (4)
14 BAR1 (4)
18 BAR2 (4)
1C BAR3 (4)
20 BAR4 (4)
24 BAR5 (4)
28 CardBus CIS Pointer (1)
2C Subsystem ID (3) Subsystem Vendor ID (3)
30 Expansion ROM Base Address (2)
34 Reserved (1) Capabilities Pointer (3)
38 Reserved (1)
3C Max Latency (1) Min Grant (1) Interrupt Pin (1) Interrupt Line (2)
+18 Reserved (1) Mem Limit Upper (2) Mem Base Upper (2)
Notes to Table 3–12 :
(1) The configuration register is not used by the HT specification. The register is a read-only register, and Read returns 0s.
(2) The register is not supported in the HyperTransport MegaCore function. The register is a read-only register and Read returns 0s.
(3) The register is a read-only register in the HyperTransport MegaCore function.
(4) The register is read/write in the HyperTransport MegaCore function.