Altera Arria II GX FPGA User Manual
Page 46

A–6
Appendix A
Restoring the MAX II CPLD to the Factory Settings
Arria II GX FPGA Development Kit User Guide
February 2011
Altera Corporation
2. Launch the Quartus II Programmer.
3. Click Auto Detect.
4. Click Add File and select
dir>\kits\arriaIIGX_2agx125_fpga\factory_recovery\max2.pof.
5. Turn on the Program/Configure option for the added file.
6. Click Start to download the selected configuration file to the MAX II CPLD.
Configuration is complete when the progress bar reaches 100%.
f
To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the
page of the Altera
website.
This manual is related to the following products:
See also other documents in the category Altera Measuring instruments:
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- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
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- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
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- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
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- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
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- Avalon Verification IP Suite (224 pages)
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- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
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- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)