Altera Arria II GX FPGA - Manual (Page 35)

Chapter 6: Board Test System 6–15
Using the Board Test System
February 2011 Altera Corporation Arria II GX FPGA Development Kit User Guide
■ Memory —Selects a generic data pattern stored in the on chip memory of the
Arria II GX device.
■ Math —Selects data generated from a simple math function within the FPGA
fabric.
W/R Control
This control specifies the type of transactions to analyze. The following transaction
types are available for analysis:
■ Write/Read —Selects read and write transactions for analysis.
■ Read Only —Selects read transactions for analysis.
■ Write Only —Selects write transactions for analysis.
The HSMC Tab
The HSMC tab allows you to perform loopback tests on the HSMC port. Figure 6–8
shows the HSMC tab.
Figure 6–8. The HSMC Tab