Altera Arria II GX FPGA - Manual (Page 30)

6–10 Chapter 6: Board Test System
Using the Board Test System
Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation
The SSRAM Tab
The SSRAM tab allows you to read and write SRAM and flash memory on your
board.
Figure 6–5 shows the SSRAM tab.
The following sections describe the controls on the SSRAM tab.
Read
This control allows you to read and write the SRAM on your board. Type a starting
address in the text box and click Read. Values starting at the specified address appear
in the table. The base address of SRAM in this Nios II-based BTS design is
0x0D00.0000. The valid address range within the 2-MB SRAM is 0x0000.0000 through
0x001F.FFFF, as shown in the GUI.
1
If you enter an address outside of the 0x0000.0000 to 0x001F.FFFF SRAM address
space, a warning message identifies the valid SRAM address range.
Figure 6–5. The SSRAM Tab