Altera Arria II GX FPGA - Manual (Page 45)

Appendix A A–5
Restoring the MAX II CPLD to the Factory Settings
February 2011 Altera Corporation Arria II GX FPGA Development Kit User Guide
5. Click Start to download the selected configuration file to the FPGA. Configuration
is complete when the progress bar reaches 100%. The CONF DONE LED (D14)
and the four user LEDs (D7-D10) illuminate indicating that the flash device is
ready for programming.
6. On the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II
Command Shell .
7. In the Nios II command shell, navigate to the
dir>\kits\arriaIIGX_2agx125_fpga\factory_recovery directory and type the
following command to run the restore script:
./restore.sh
r
Restoring the flash memory might take several minutes. Follow any instructions
that appear in the Nios II command shell.
8. After all flash programming completes, cycle the POWER switch (SW1) off then
on.
9. Using the Quartus II Programmer, click Add File and select
dir>\kits\arriaIIGX_2agx125_fpga\factory_recovery\ArriaIIGX_2agx125_dev_
bup.sof
.
10. Turn on the Program/Configure option for the added file.
11. Click Start to download the selected configuration file to the FPGA. Configuration
is complete when the progress bar reaches 100%. The CONF DONE LED (D14)
and the four user LEDs (D7-D10) illuminate indicating the flash memory device is
now restored with the factory contents.
12. Cycle the POWER switch (SW1) off then on to load and run the restored factory
design.
13. The restore script cannot restore the board’s MAC address automatically. In the
Nios II command shell, type the following Nios II EDS command:
nios2-terminal
r
and follow the instructions in the terminal window to generate a unique MAC
address.
f To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the
Arria II GX FPGA Development Kit page of the Altera
website.
Restoring the MAX II CPLD to the Factory Settings
This section describes how to restore the original factory contents to the MAX II CPLD
on the FPGA development board. Make sure you have the Nios II EDS installed, and
perform the following instructions:
1. Set the board switches to the factory default settings described in “Factory Default
Switch Settings” on page 4–2 .
1 Uninstalling the shunt jumper from jumper J9 pins 1-2 includes the MAX II
device in the JTAG chain.