Altera Arria II GX FPGA - Manual (Page 37)

Chapter 6: Board Test System 6–17
Using the Board Test System
February 2011 Altera Corporation Arria II GX FPGA Development Kit User Guide
■ Memory —Selects a generic data pattern stored in the on chip memory of the
Arria II GX device.
■ Math —Selects data generated from a simple math function within the FPGA
fabric.
Error Control
This control displays data errors detected during analysis and allows you to insert
errors:
■ Detected Errors —Displays the number of data errors detected in the hardware.
■ Inserted Errors —Displays the number of errors inserted into the transmit data
stream.
■ Insert Error —Inserts a one-word error into the transmit data stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
■ Clear —Resets the Detected errors and Inserted errors counters to zeros.
Start
This control initiates HSMC transaction performance analysis.
Stop
This control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
■ TX and RX performance bars—Show the percentage of maximum theoretical data
rate that the requested transactions are able to achieve.
■ Tx (MBytes/s) and Rx (MBytes/s)—Show the number of bytes of data analyzed
per second. The HSMA transceiver bus is 4 bits wide and the data rate is
3.75 Gbps, totaling 1.5625 GBps full-duplex. The LVDS SERDES bus is 17 bits
wide. The transmit data bus is 16 bits wide and the frequency is 300 MHz double
data rate (600 Mbps per pin), equating to a theoretical maximum bandwidth of
1200 MBps.