Altera Arria II GX FPGA - Manual (Page 36)

6–16 Chapter 6: Board Test System
Using the Board Test System
Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation
1 You must have the loopback HSMC installed on the HSMC connector that you are
testing for this test to work correctly.
The following sections describe the controls on the HSMC tab.
Status
This control displays the following status information during the loopback test:
■ PLL lock —Shows the PLL locked or unlocked state.
■ Channel lock —Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded.
■ Pattern sync —Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Port
This control allows you to specify the type of test to run on the HSMC ports. The
following HSMC port tests are available:
■ HSMA x4 Tranceivers [0..3]
■ HSMA x17 LVDS SERDES
■ HSMA x3 single-ended loopback
PMA Setting
The PMA Setting button allows you to make changes to the PMA parameters that
affect the active transceiver interface. The following settings are available for analysis:
■ Serial Loopback —Routes signals from the receiver to the transmitter.
■ VOD —Specifies the voltage output differential of the transmitter buffer.
■ Pre-emphasis tap
■ Pre —Specifies the amount of pre-emphasis on the pre-tap of the transmitter
buffer.
■ First post —Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
■ Second post —Specifies the amount of pre-emphasis on the second post tap of
the transmitter buffer.
■ Equalizer —Specifies the setting for the receiver equalizer.
■ DC gain —Specifies the DC portion of the receiver equalizer.
f For restrictions on the PMA settings, refer to Volume 2: Transceivers of the Arria II
Device Handbook.
Data Type
This control specifies the type of data contained in the transactions. The following
data types are available for analysis:
■ PRBS —Selects pseudo-random bit sequences.