Altera Embedded Systems Development Kit, Cyclone III Edition - Manual (Page 41)

6–3 Development Board Version 1.0. Altera Corporation
Altera Embedded Systems Development Kit, Cyclone III Edition July 2010
About the Nios II 3C120 General Purpose Microprocessor System
CPU Platform
The CPU platform consists of
■ Nios II/f cpu core
■ JTAG Debug Port
■ 32KB Instruction Cache
■ 32KB Data Cache
Memory Interfaces
■ DDR2 SDRAM Controller
● Run time program and data memory
■ CFI Flash Controller
● Stores FPGA configuration data
Communication Interfaces
■ JTAG UART
● Used for Serial communication and debugging Nios II
applications via the on-board USB-Blaster circuitry.
Peripheral Set
■ PLL
● Accepts the global input clock source from the 50MHz on-board
oscillator and generates the following clocks
● 100 MHz CPU Clock
● 60 MHz Peripheral Clock (“slow peripherals”)
■ System Clock Timer
● General purpose system timer.
■ Performance Counter
● Counter used for debug and system performance analysis.
■ System ID
● Used to sync the hardware system generation with the software
generation tools.
■ Max II Interface
● Communicates with the Max II CPLD on the base board. The
Max II CPLD manages configuration of the FPGA on boot up
using Fast Passive Parallel (FPP) configuration scheme.
■ LED PIO
● Output only control block for LED1-LED4
■ Pushbutton PIO
● Input only control block for the on-board pushbuttons.
■ PIO for ID EEPROM (I2C)
● Used to communicate with the EEPROM ID chip which stores
information about the board