Altera Embedded Systems Development Kit, Cyclone III Edition User Manual
Page 32
Altera Corporation
Development Board Version 1.0.
4–4
July 2010
Altera Embedded Systems Development Kit, Cyclone III Edition
Remote System Update Via Ethernet
■
On your host PC, launch a Nios II Command Shell from Start ->
Programs -> Altera -> Nios II <
version> EDS -> Nios II Command
Shell
■
From the command shell navigate to where your SOF file is located
and create your hardware Flash image using the following
command:
●
sof2flash --compress --input="your SOF.sof" --
output="your SOF.flash" --offset=0x3880000.
■
From the command shell navigate to where your ELF file is located
and create your software Flash image using the following command:
elf2flash --base=0x10000000 --end=0x013FFFFFF --
reset=0x10240000 --input="your ELF.elf" --
boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_
loader_cfi.srec
If you need to update more images (hardware or software) click the main
hyperlink (takes you back to the main/index page) and repeat step 1-3 as
necessary.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)