Altera Embedded Systems Development Kit, Cyclone III Edition - Manual (Page 40)

Altera Corporation Development Board Version 1.0. 6–2
July 2010 Altera Embedded Systems Development Kit, Cyclone III Edition
Example Processor Systems
Description
Simple general purpose Nios II-based processor system targeted for the
Altera Embedded Systems Development Kit, Cyclone III Edition that
includes a CPU, DDR2 Memory controller, timers, PLLS and other
peripherals. The processors system can easily be modified using SOPC
Builder or added to your existing Quartus II project as a component.
IP licenses required to Ship design
Most of the IP cores used in this design require no licensing. The
following IP licenses however are required to ship design:
■ Nios II IP evaluation license with Nios II EDS
■ DDR2 SDRAM memory controller core shipping license from Altera
1
For more information on how to obtain evaluation or
shipping licenses for the above refer to
“Licensing IP” on
page 2–4 .
Nios II 3C120 General Purpose Microprocessor System
Description
The components in the Nios II 3C120 standard microprocessor system are
shown in
Figure 6–1 .
Figure 6–1. Nios II 3C120 General Purpose Microprocessor Systems Block Diagram
CPU Platform
System Functions
Nios II /f
CPU
Core
JTAG
Debug
32 KB
I-Cache
32 KB
D-Cache
PLL/
System
Clock
Perfor-
mance
Counter
System
ID
Remote
Update
Memory Interface
2x64MB
DDR
64 MB
Flash
Communications Interface
JTAG
UART
UART
System Peripherals
Push
Button
PIO
LED PIO
Nios II 3C120 General Purpose Processor System
(Standard)