Maxim Integrated 73S12xxF - Manual (Page 36)

Using Synchronous Smart Cards with the 73S12xxF UG_12xxF_018
36 Rev. 1.0
Write 9 to RLEN
Set receive and I 2 C mode,
set TX/RXB and SYCKST
bits in STXCtl
Wait for smart card Interrupt
Read SCInt
WAITTO bit
set?
No
Yes
G
H
Enable WAITTO interrupt,
Set WAITTO bit in SCIE
Wait for smart card Interrupt
Read SCInt
WAITTO bit
set?
No
Yes
Internal logic is set up to read I/O and route it to the IO
bit in the SCCtl register during the ACK bit slot (when
operating in I
2 C mode). The IOD bit must be set for
input during the ACK bit slot. The I/O signal will output
the transmit data at all other times.
Set I/O for input/high and
leave CLK running,
clear CLKOFF and set
IO,IOD bits in SCCtl
Delay 1/2 ETU
ACK bit clear?
Yes
No
Process ACK error and try
again
Delay 1/2 ETU
Internal logic is set up to output the contents of the I/O bit
in the SCCtl register and route it to the IO pin during the
ACK bit slot (when operating in I
2 C mode) when reading
data from the card. The IOD bit must be set for output
during the ACK bit slot. The I/O signal will input the
receive data at all other times.
Set I/O for outut/low and
leave CLK running,
clear CLKOFF, IOD and
IO bits in SCCtl
Delay a minumum of 1/2 ETU to allow ACK bit slot
to complete.
F