Maxim Integrated 73S12xxF - Manual (Page 11)

UG_12xxF_018 Using Synchronous Smart Cards with the 73S12xxF
Rev. 1.0 11
3.2.1 2-Wire Card Operation
3.2.1.1 ATR Retrieval
The description of the ATR sequence for 2-wire cards is described in Section 2.2.1 . A scope capture for
the ATR is shown in Figure 11 . Note that the RST is high during the first clock pulse. As mentioned
before, since the first edge of the CLK is a rising one, the data on the I/O is undefined. This is no problem
as it is a don’t care during reset. The first falling edge will configure the RX FIFO to receive the first bit
from the card and the next rising edge will sample the data. The flowchart for retrieving the ATR is shown
in
Figure 25 . This flowchart includes the steps necessary for initializing the CLK output low, making sure
the card is inserted (or activation is blocked by hardware), turning on the card supply (VCC), generation
of the RST pulse, reading the four byte ATR value and stopping the CLK when done.
Figure 11: ATR Scope Capture
3.2.1.2 Sending Commands
2-wire card commands must follow the format as described in Section 2.1.2 . The sequence must begin
with a start bit and end with a stop bit. An entire command frame shown in Figure 12 . A zoom of the start
bit located at the left cursor of Figure 12 is shown in Figure 13 . A zoom of the stop bit located at the right
cursor of Figure 12 is shown in Figure 14.
Figure 12: Command Frame