Maxim Integrated 73S12xxF - Manual (Page 10)

Using Synchronous Smart Cards with the 73S12xxF UG_12xxF_018
10 Rev. 1.0
3 Using Synchronous Smart Cards with the 73S12xxF
The smart card block within the 73S12xxF device contains specific support for synchronous smart cards.
See the “Synchronous Operation Mode” section of the specific 73S12xxF data sheet for a description of
the differences between Asynchronous and Synchronous operation within the smart card block. The
purpose of this application note is to describe how the smart card block should be used to operate a
synchronous smart card.
3.1 Special Precautions when Using Synchronous Smart Cards
3.1.1 Synchronous Mode Clock
The CLK output is sourced by the ETU clock. The ETU clock is a free running clock that can’t be started
or stopped. As a result, the CLK output is not initialized and must be set to a high or low level before any
synchronous transaction can begin. The level is determined by the card type being used. The CLK
output must be started and allowed to run for a full clock cycle and then stopped at the desired logic level
manually. This is not desirable during a card session, so it is recommended to perform this initialization
before the card is activated. This can be done before turning on VCC to the card. The CLK output will
always be at ‘0’ when VCC is off, but the smart card logic remains active. The procedure for initializing
the CLK output is as follows: Note: this procedure is only necessary from a power on or device reset
condition as the CLK will be stopped after any card transaction.
1. Turn on the CLK by writing ‘0’ to the CLKOFF bit in the SCCtl register.
2. Wait a minimum of 1 ETU. This is necessary to ensure that both CLK edges are seen by the logic
and allowed to stop the output at the desired level.
3. Set CLKLVL to the desired logic level and write ‘1’ to the CLKOFF bit to stop the CLK output at the
desired level.
4. Turn on VCC to the desired voltage.
For all synchronous transactions, the data is shifted to/from the data FIFOs on the falling edge of CLK
and the data is read or written on the rising edge. The CLK logic must output a falling edge on CLK to
properly configure the FIFOs for read or write operations. If the first edge of the CLK output is rising (after
being started), this edge is ignored and the next rising edge will sample the first bit of the data. It should
be noted that the RLEN counter is incremented on the falling edge of CLK.
3.1.2 Proper Use of Interrupts in Synchronous Mode
When operating with Asynchronous cards, the transmit buffer empty and receive register full are used to
control the interrupt processing for data transfer. When using synchronous cards, these interrupts should
not be used. Instead, the clock counter (RLEN) should be used to keep track of the number of clock
pulses output on CLK. The best way to perform data transactions is to send data on a byte by byte basis
since the data FIFOs are byte wide. Setting the RLEN register to 8 will accomplish this. This way the
interrupts are generated when the FIFO is emptied or filled. The value that is written to RLEN will need to
be something other than 8 due to CLK limitations described above. These exceptions will be explained
later in this document.
3.2 73S12xxF Operation
The following sections describe how the three different synchronous smart card types operate with the
73S12xxF. Each section describes how the ATR is retrieved (when applicable), how to send commands
to the card and read data from the card. Refer to the flowcharts in
Appendix A .