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Cypress enCoRe CY7C602xx User Manual

Page 62

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CY7C601xx, CY7C602xx

Document 38-16016 Rev. *E

Page 62 of 68

Figure 20-4. SPI Slave Timing, CPHA = 1

Figure 20-5. SPI Master Timing, CPHA = 0

MSB

T

SSU

LSB

T

SHD

T

SCKH

T

SDO

SS

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

MISO

T

SCKL

T

SSS

T

SSH

MSB

LSB

MSB

T

MSU

LSB

T

MHD

T

SCKH

T

MDO1

SS

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

MISO

(SS is under firmware control in SPI Master mode)

T

SCKL

T

MDO

LSB

MSB

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