Cypress enCoRe CY7C602xx - Manual (Page 53)

CY7C601xx, CY7C602xx
Document 38-16016 Rev. *E Page 53 of 68
Figure 18-4. 16-Bit Free Running Counter Loading Timing Diagram
Figure 18-5. Memory Mapped Registers Read and Write Timing Diagram
clk_sys
write
valid
addr
write data
FRT reload
ready
Clk Timer
12b Prog Timer
12b reload
interrupt
Capture timer
clk
16b free running
counter load
16b free
running counter
00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0
16-bit free running counter loading timing
12-bit programmable timer load timing
Memory mapped registers Read/Write timing diagram
clk_sys
rd_wrn
Valid
Addr
rdata
wdata
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