Digilent DIO5 - Manual (Page 13)

DIO5 Reference Manual Digilent, Inc.
www.digilentinc.com Page 13
Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners.
the frequency at which all information on the
display is redrawn. The minimum refresh
frequency is a function of the display’s
phosphor and electron beam intensity, with
practical refresh frequencies falling in the 50Hz
to 120Hz range. The number of lines to be
displayed at a given refresh frequency defines
the horizontal “retrace” frequency. For a 640-
pixel by 480-row display using a 25MHz pixel
clock and 60 +/-1Hz refresh, the signal timings
shown in the table below can be derived.
Timings for sync pulse width and front and
back porch intervals (porch intervals are the
pre- and post-sync pulse times during which
information cannot be displayed) are based on
observations taken from VGA displays. A VGA controller circuit decodes the output of a
horizontal-sync counter driven by the pixel clock
to generate HS signal timings. This counter can
be used to locate any pixel location on a given
row. Likewise, the output of a vertical-sync
counter that increments with each HS pulse can
be used to generate VS signal timings, and this
counter can be used to locate any given row.
These two continually running counters can be
used to form an address into video RAM. No
time relationship between the onset of the HS
pulse and the onset of the VS pulse is specified,
so the designer can arrange the counters to
easily form video RAM addresses, or to minimize
decoding logic for sync pulse generation.
XCR3128XL CoolRunner CPLD
The CPLD is in a TQ144 package that has 108
user I/Os available. Of these, 63 are routed to
devices on the DIO5, 17 are assigned to form
a “system bus” that connects the DIO5 and a
system board, 10 connect pushbutton signals
directly to a system board, 6 are uncommitted
I/O signals routed to the system board, and 2
are used to pass PS/2 port signals through to a
system board. The remaining 10 signals are
not connected. CPLD pinouts are shown in the
table below.
The CPLD can contain various controller
circuits to pass DIO5 device signals to an
attached system board. During manufacturing,
the CPLD is configured with the register-based
circuit shown in the Appendix, but the CPLD
can easily be configured with other circuits.
JTAG programming signals are routed across
the expansion connectors from the D2-SB, D2-
FT, and other system boards, so the CPLD can
be configured whenever the DIO5 is attached to
one of these boards. The CPLD will appear in
the scan chain when shorting blocks are loaded
on pins 1 & 2 of jumpers JP2 & JP3 (conversely,
if shorting blocks are loaded on pins 2 and 3, the
CPLD will not appear in the scan chain). The
center pins of JP2 & JP3 should not be left
floating – jumpers should always be loaded
across pins 1 & 2 or across pins 2 & 3.
Expansion Connectors
The connector pinouts are shown below.
Separately available tables show pass-through
connections for the devices on the DIO5 board
when it is attached to various system boards.
T
S
T
disp
T
pw
T
fp
T
bp
T
S
T
disp
T
pw
T
fp
T
bp
Sync pulse time
Display time
VS pulse width
VS front porch
VS back porch
16.7ms
15.36ms
64 us
320 us
928 us
416,800
384,000
1,600
8,000
23,200
521
480
2
10
29
Symbol Parameter
Time Clocks Lines
Vertical Sync
32 us
25.6 us
3.84 us
640 ns
1.92 us
800
640
96
16
48
Clocks
Horizontal Sync
Time