Digilent 410-274P-KIT - Manual (Page 5)

Nexys4™ FPGA Board Reference Manual
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Page 5 of 29
Bitstreams are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA’s logic functions
and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset
button attached to the PROG input, or by writing a new configuration file using the JTAG port.
An Artix-7 100T bitstream is typically 30,606,304 bits and can take a long time to transfer. The time it takes to
program the Nexys4 can be decreased by compressing the bitstream before programming, and then allowing the
FPGA to decompress the bitsream itself during configuration. Depending on design complexity, compression ratios
of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools (ISE or Vivado) to occur
during generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.
After being successfully programmed, the FPGA will cause the "DONE" LED to illuminate. Pressing the “PROG”
button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately
attempt to reprogram itself from whatever method has been selected by the programming mode jumpers.
The following sections provide greater detail about programming the Nexys4 using the different methods
available.
2.1 JTAG Programming
The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture,
commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using
the onboard Digilent USB-JTAG circuitry (port J6) or an external JTAG programmer, such as the Digilent JTAG-HS2,
attached to port J10. You can perform JTAG programming any time after the Nexys4 has been powered on,
regardless of what the mode jumper (JP1) is set to. If the FPGA is already configured, then the existing
configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG
setting (seen in Fig 3) is useful to prevent the FPGA from being configured from any other bitstream source until a
JTAG programming occurs.
Programming the Nexys4 with an uncompressed bitstream using the on-board USB_JTAG circuitry usually takes
around five seconds. JTAG programming can be done using the hardware server in Vivado or the iMPACT tool
included with ISE and the labtools version of Vivado. The demonstration project available at digilentinc.com gives
an in depth tutorials on how to program your board.
2.2 Quad-SPI Programming
When programming a nonvolatile flash device, a bitstream file is transferred to the flash in a two-step process.
First, the FPGA is programmed with a circuit that can program flash devices, and then data is transferred to the
flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). After the flash device
has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as
determined by the mode jumper setting (see Fig 3). Programming files stored in the flash device will remain until
they are overwritten, regardless of power-cycle events.
Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process
inherent to the memory technology. Once written however, FPGA configuration can be very fast-- less than a
second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilnx tools that
can affect configuration speed.