Chapter 1, Sbus overview, Introduction – Achronix Speedster22i sBus User Manual
Page 9: Figure 1: the hd1000 fpga with sbus interfaces, Chapter 1 – sbus overview, Hd1000
UG047, October 24, 2013
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Chapter 1
– sBus Overview
In this chapter, you will learn the following about the sBus serial bus:
Introduction
The sBus is a serial bus on the Achronix AC22IHD1000-F53C3 (“HD1000”) FPGA to enable
designers to communicate with registers on the Ethernet, SerDes, PCIe, Interlaken, and DDR
hard IPs. You can write to the IP registers to configure properties and read from the registers
to verify current configuration. The sBus provides communications between the FPGA fabric
and the interfaces of the hard IPs to the FPGA fabric. The control logic for the sBus is
implemented in the FPGA fabric.
Figure 1 shows the HD1000 FPGA with the sBus highlighted.
Figure 1: The HD1000 FPGA with sBus interfaces
Note: PLL registers are 8-bit but the interface is 32-bit. Upper 24-bits are ignored.
Fabric
DDR
Interlaken
16-bit
Ethernet
MAC
32-bit
SerDes
PCIe
sBus
Port
Control
Logic
HD1000
Hard IP
Area
PLL