Achronix Speedster22i sBus - Manual (Page 22)

22 UG047, October 24, 2013
sBus Master Operation
The sBus master will move from the ST_SBUS_IDLE to the ST_SBUS_ADDR state when you
assert the i_sbus_req signal. Depending on whether the request is for a write or a read, as
determined by the state of the i_sbus_data[0] signal, the state machine will transition to
the ST_BUS_WR_DATA or ST_BUS_RD_DATA and after the completion of the cycle
transition back to the ST_BUS_IDLE state.
Clocking Considerations
Most sBus channels must be operated at under 50 MHz clock speeds. The following code
fragment shows a typical example, where the clock has been set to 16 MHz for the Ethernet
IP interface.
#### -------- CLOCK INFORMATION -------- ####
create_clock -period 10.0 pll_ref_clk
create_clock -period 62.5
{iSBUS_CLK_PLL.NE_APLL_0_gui_ne_pll_APLL.iACX_PLL/ogg_gm_clk[0]} -name
sbus_clk
######------------ DONE -----------#########