Achronix Speedster22i sBus - Manual (Page 23)

UG047, October 24, 2013 23
Appendix A
– sBus Master Verilog Code
//
// Module Name : sbus_master_if
//
// Description : SBUS master module to transfer parallel register data in
// serial mode to reduce the number of status ports.
//
module sbus_master_if #(parameter PBUS_DATA_WIDTH = 8) (
// SBUS Interface
input [1:0] i_sbus_d,
input i_sbus_ack,
output [1:0] o_sbus_d,
output o_sbus_req,
// Generic Register Interface
input i_reg_write,
input i_reg_rw_req,
input [16:0] i_reg_address,
input [PBUS_DATA_WIDTH-1:0] i_reg_wr_data,
output [PBUS_DATA_WIDTH-1:0] o_reg_rd_data,
output reg o_reg_rdwr_valid,
// Generic signals
// Reset the StateMachine if ack is not received
input i_sw_rst,
input i_clk,
input i_rst_n
);
//Function to calculate the size from the PBUS_WIDTH
// Start of Function
function integer c_log_b;
input integer depth;
integer i;
begin
c_log_b = 1;
for (i=0; 2**i < depth; i=i+1)
c_log_b = i+1;
end
endfunction
// End of Function
/////////////////////////////////////////////////
localparam CNTR_SIZE = c_log_b (PBUS_DATA_WIDTH/2);
reg [2:0] address_cnt;
reg [1:0] data_in_dly;
reg [(CNTR_SIZE-1):0] rdwr_data_cnt;
reg [4:0] sbus_cs;
reg [16:0] rw_address;
reg [PBUS_DATA_WIDTH-1:0] rd_data_shift_in,write_data;
reg [PBUS_DATA_WIDTH+17:0] addr_data_shift_in;
wire [17:0] addr_req;
reg is_write,req_dly,req_dly2,sbus_req_dly;
wire start_sbus_transfer,sbus_req;
//////////////////////////////////////////////////////////////////////
parameter ST_SBUS_IDLE = 5'b00001;