Achronix Speedster22i sBus - Manual (Page 4)

4 UG047, October 24, 2013
Read Operation ............................................................................................................................ 17
Write Operation ............................................................................................................................ 17
Single Master for Multiple Slaves Implementation ............................................................... 18
Master Specifications for Ethernet MAC and SerDes sBus Controller .......................................... 18
Master Actions for Ethernet MAC and SerDes sBus Controller .................................................... 18
Read Operation ............................................................................................................................ 18
Write Operation ............................................................................................................................ 18
Design Considerations ................................................................................................................. 18
Multiple Masters for a Single/Multiple Slave(s) Implementation ........................................... 19
Design Considerations ................................................................................................................. 19
Chapter 5
– sBus Design Examples ............................................................... 20
sBus Master Design ............................................................................................................. 20
Design Example ........................................................................................................................... 20
Master State Machine .................................................................................................................. 21
sBus Master Operation ........................................................................................................ 22
Clocking Considerations ...................................................................................................... 22
Appendix A
– sBus Master Verilog Code....................................................... 23
Appendix B
– Revision History ...................................................................... 27