Achronix Speedster22i sBus - Manual (Page 18)

18 UG047, October 24, 2013
3. Monitor the o_sbus_ack signal from the PLL sBus slave signaling the end of the write
request.
Note: You can simplify your design to send a fixed data pattern for the upper 24-bits.
4. Inform the user on the fabric side of the completion of the write request.
Single Master for Multiple Slaves Implementation
You can use a single sBus master to communicate with multiple sBus slaves on a hardened IP
such as the Ethernet MAC and SerDes on the HD1000. You can get more information about
the slave interfaces for the specific IP from the relevant User Guide. In the case of the
Ethernet MAC and the associated SerDes, the master must have the following specifications.
Master Specifications for Ethernet MAC and SerDes sBus
Controller

32-bit data width for the MAC

8-bit data width for the 12 SerDes

104 (8 x 13) pins to drive each of the 13 Ethernet sBus slave interfaces

Pins to receive the register programming information from the user on the fabric side

Pins to provide register/status information to the user on the fabric side
Master Actions for Ethernet MAC and SerDes sBus Controller
Read Operation
1. Receive information from the user for the read request on the fabric side.
2. Drive the read actions on the sBus.
a. 32-bit Data-width Mode for the MAC registers
b. 8-bit Data-width Mode for the SerDes registers
3. Monitor the o_sbus_ack signal from the appropriate IP block to accept the serial data from
the sBus slave.
4. Latch the serial data and provide it to the user on the fabric side.
Write Operation
1. Receive information from the user for the write request on the fabric side.
2. Drive the write actions on the sBus.
a. 32-bit Data-width Mode for the MAC registers
b. 8-bit Data-width Mode for the SerDes registers
3. Monitor the o_sbus_ack signal from the appropriate IP sBus slave signaling the end of the
write request.
4. Inform the user on the fabric side of the completion of the write request.
Design Considerations
Depending on your application and the register(s) accessed, you may have to take additional
actions to ensure predictable behavior of the IP core and your application. For example, you
may have to ensure that all the SerDes registers are updated before transmissions based on
the new configuration are started. If multiple registers in different IP blocks require updates