Achronix Speedster22i sBus - Manual (Page 10)

10 UG047, October 24, 2013
Operation
The sBus takes serial data from the FPGA fabric sBus control logic (“Fabric”) and transmits it
over a 2-bit data bus to the hard IP sBus interface for writes. For reads, the sBus takes 2-bit
serial data from the hard IP to the Fabric. During a write operation, the Fabric converts the
parallel data, 8-, 16-, or 32-bit wide and serializes it. The Fabric presents the address of the
register to be written to and the data to the IP interface over the 2-bit serial bus. For read
operations, the Fabric presents the address for the read operation to the IP interface and the
the hard IP responds by placing the 2-bit serialized data on the sBus.
The sBus can operate such that a single IP is accessed or in a master-slave mode such that
multiple IPs can be accessed.
Figure 2 shows the signals used for communications between the Fabric and the hard IP,
which includes the logic to receive and convert the write address and data to the correct
format for updating the registers. For reads, the register data is converted from parallel to
serial for presentation to the sBus by the hard IP block.
Figure 2: The sBus interface signals
Features
Bus

2-bit serial data width

8-, 16-, or 32-bit parallel data

Single clock
Accessible IPs

Ethernet

SerDes

PCIe

Interlaken

DDR

PLL
Hard IP
sBus
Port
Fabric
sBus Port
Control
Logic
sbus_clk
reset_sbus_clk
i_sbus_req
i_sbus_data[1:0]
o_sbus_ack
o_sbus_data[1:0]
R
e
g
is
te
rs