Achronix Speedster22i sBus - Manual (Page 7)

UG047, October 24, 2013 7
Preface
About this Guide
The Achronix sBus is a serial bus implemented on the AC22IHD1000-F53C3 FPGA device to
allow users to access configuration registers for several of the Hard IPs available on the
device, through the FPGA fabric. This guide provides details on the implementation and uses
of the sBus. You will learn about the IP control registers that can be configured, status
registers, and how to access them for reads and writes, using the sBus, as appropriate.
Examples are provided to help you with the implementation of your own system designs.
This guide consists of the following chapters:
Chapter 1 – sBus Overview provides an overview of the sBus implemented on the
AC22IHD1000-F53C3 FPGA device.
Chapter 2 – sBus Functional Description covers more details of the sBus functionality.
Chapter 3 – sBus Interfaces describes the master and slave interfaces for the sBus.
Chapter 4 – sBus Master Implementation provides information about designing with the
sBus functional block.
Chapter 5 – sBus Design Examples provides detailed design examples for a single and
multiple IP access.
Appendix A – sBus Master Verilog Code provides a code example for a sample sBus
master design.
Appendix B – Revision History highlights the revisions to this document.
Target Readership (or Audience)
This guide is intended for embedded systems and sub-systems designers working with the
Achronix HD1000, 22-nm FPGA. You should have knowledge of FPGAs, Controllers,
Development environments and other relevant technologies.
This guide does not include board design and layout information. If you want assistance with
board design and layout, please contact Achronix.
Reference Documents
Speedster22i FPGA Family Datasheet (DS004)
Speedster22i Development Kit User Guide (UG034)
ACE User Guide (UG001)
Achronix Software & License User Guide (UG002)
Bitporter User Guide (UG004)