Achronix Speedster22i DDR - Manual (Page 7)

Introduction
Speedster22i devices contain up to six embedded (Hardened) DDR Controllers. The
instantiatable macros for these are called ‘ddr3_xSIZE 1 _LOCATION 2 ’ where size can be
configured as 72,64,32,16 or 8 and location can be EN,EC,ES,WN,WC,WS for a device with
six controllers, such as the Speedster22i HD1000. Each Macro is comprised of a DDR
Controller and a DDR PHY, and is controlled by the user by means of the DDR driver logic.
The DDR3 controller macros manage the interface between the DDR driving logic (housed
within the Core Fabric) and the off-chip DDR memory itself. A more detailed description of
these interfaces is illustrated in Figure 2 below.
Speedster22i
DDR Control Macro
ACX_PLL
DDR
Controller
clk
sd_dummy[8:0]
sd_dm[8:0]
sd_dqsn[8:0]
sd_dqsp[8:0]
sd_dq[71:0]
sd_cke[3:0]
sd_clk_out_p[3:0]
sd_clk_out_n[3:0]
sd_reset_n
sd_cas_n
sd_ras_n
sd_we_n
sd_a[15:0]
sd_ba[2:0]
sd_cs_n[3:0]
sd_odt[3:0]
Read/Write
Shared Interface
Write Interface
Read Interface
General Memory
Control Interface
Manual refresh
control Interface
Control
Interface
DDR Internal Interface
(User Logic)
ddr_int_clk_div2
ddr_int_zq_cal_ack
ddr_int_ref_ack
ddr_int_busy_align
ddr_int_busy
ddr_int_wrdata_valid
ddr_int_wrdata_req[8:0]
ddr_int_wrdata_req_early[8:0]
ddr_int_wrdata_req_align[8:0]
ddr_int_wrdata_req_early_align[8:0]
ddr_int_rddata[287:0]
ddr_int_rddata_valid [8:0]
ddr_int_rddata_valid_align[8:0]
ddr_int_rddata_valid_early[8:0]
ddr_int_rddata_valid_early_align[8:0]
ddr_int_init_ack
ddr_int_init_wlvl_done
ddr_int_cmd_auto_pch
ddr_int_cmd_self_refresh[1:0]
ddr_int_addr[33:0]
ddr_int_burst_size[7:0]
ddr_int_wr_request
ddr_int_wrdata[287:0]
ddr_int_wrdata_mask[17:0]
ddr_int_rd_request
reset_ddr_ctrlr_n
reset_ddr_phy_n
ddr_int_phy_ci_slave_dqsn_en
ddr_int_cmd_power_down[1:0]
ddr_int_cmd_ref_req
ddr_int_cmd_zq_cal_req[1:0]
ddr_int_phy_ci_slave_adj
DDR
PHY
External
DDR Memory
Figure 2: Top-level Overview of Embedded DDR Control Logic
UG031, Nov 18, 2014 7