Achronix Speedster22i DDR - Manual (Page 28)

The read requests are subject to the controller being busy (‘ddr_int_busy_align’).
The DDR controller supports burst length option BL8. Each burst will contain a single local
side transfer, which is equivalent to 8 transfers from the DDR memory.
Speedster22i
DDR
Controller
ddr_int_rd_request
ddr_int_addr[33:0]
ddr_int_burst_size[7:0]
ddr_int_busy_align
ddr_int_rddata_valid_early_align
ddr_int_rddata_valid_align
ddr_int_rddata[575:0]
clk_div4
DDR Driver
Logic
(in Core Fabric)
Figure 17: Read Interface with Wide Bus Interface Enabled
The following timing diagram illustrates a single read command of burst length 4. The
signals shown in the following diagrams are ports at the (‘ddr3_xSIZE 1 _LOCATION 2 ’. Where
1: SIZE = 72, 64, 32, 16, 8 and 2: LOCATION=EN, EC, ES, WN, WC, WS).
clk_div4
ddr_int_rd_ request
a 0 ddr_int_ addr[33:0]
ddr_int_ busy_ align
d0
ddr_int_ rddata_ valid_ align
ddr_int_ rddata[ 575:0]
Valid Read Command
4 ddr_int_ burst_size[7:0]
Timing relationship between ddr_int_rd_request and
ddr_int_rddata_valid assertion based on AL/CL configuration
settings, refresh status and status of bank/row begins assessed
Figure 18: Internal Interface Read Protocol Timing Diagram with Wide Bus Interface Enabled
28 UG031, Nov 18, 2014