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Table of Figures
Figure 1: Location of Speedster22i DDR Controllers and PHYs ............................................................... 5
Figure 2: Top-level Overview of Embedded DDR Control Logic ............................................................... 7
Figure 3: Address mapping of ‘ddr_int_addr’ Signal ............................................................................... 14
Figure 4: Write Interface 2X Clock Mode ................................................................................................. 15
Figure 5: Internal Interface Write Protocol Timing Diagram .................................................................. 16
Figure 6: Internal Interface Write Protocol Timing Diagram with default value ‘addrcmd_delay’ to 8 . 17
Figure 7: Write Protocol Timing Diagram (SDRAM Interface) ............................................................... 18
Figure 8: Write Protocol Timing Diagram (Write requests with valid writes highlighted)...................... 19
Figure 9: Write Protocol Timing Diagram (ddr_int_wrdata_req corresponding to respective writes highlighted) ............................................................................................................................................... 20
Figure 10: Write Interface with Wide Bus Interface Enabled ................................................................... 22
Figure 11: Internal Interface Write Protocol Timing Diagram with Wide Bus Interface Enabled .......... 22
Figure 12: Read Interface 2X Clock Mode ............................................................................................... 24
Figure 13: Internal Interface Read Protocol Timing Diagram ................................................................. 24
Figure 14: External Interface Read Protocol Timing Diagram ................................................................ 25
Figure 15: Read Protocol Timing Diagram (with valid read request highlighted) .................................. 26
Figure 16: Read Protocol Timing Diagram (with ddr_int_rddata_valid highlighted) ............................. 26
Figure 17: Read Interface with Wide Bus Interface Enabled ................................................................... 28
Figure 18: Internal Interface Read Protocol Timing Diagram with Wide Bus Interface Enabled ........... 28
Figure 19: DDR3 Customization using ACE ............................................................................................ 31
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UG031, Nov 18, 2014
