Achronix Speedster22i Interlaken - Manual (Page 6)

Introduction
Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds
from 10Gbps to 100Gbps and beyond. Using the latest SerDes technology and a flexible protocol
layer, Interlaken minimizes the pin and power overhead of chip-to-chip interconnect and
provides a scalable solution that can be used throughout an entire system. In addition, Interlaken
uses two levels of CRC checking and a self-synchronizing data scrambler to ensure data integrity
and link robustness.
The Achronix Interlaken IP Core (IIPC) is available as hard IP in Speedster22i devices. The IIPC is
a high-performance, low-power and flexible implementation of the Interlaken Protocol. The IIPC
is compliant with the Interlaken Protocol Definition, Revision 1.2, and offers system designers
with a risk-free and quick path for adopting Interlaken as their chip-to-chip interconnect
protocol. The IIPC can be configured to use any number of serial lanes (between 4 to 12) for an
aggregate bandwidth of up to 123 Gbps.
The rest of this document describes the IIPC in detail and provides the information required for
the user to integrate the IIPC into their designs. The document assumes the reader is familiar
with the Interlaken protocol and FPGA design and methodology.
Interlaken is a very flexible and customizable protocol. IIPC supports the following features:
• Designed to take full advantage low-power design flows and methodology
• Automatic scaling of clocks to minimize power consumption
• Support for up to 10.3125Gbps SerDes data rate
• Support for 256 different logical channels
• Robust error condition detection and recovery
• Flexible SerDes interface to accommodate different I/O implementations
• Data striping and de-striping across 4 to 12 lanes
• Programmable BurstMax, BurstShort and MetaFrameSize parameters
• 64/67 encoding and decoding
• Automatic word and lane alignment
• Self-synchronizing data scrambler
• Data bus width of 512 bits
• CRC24 generation and checking for burst data integrity
• CRC32 generation and checking for lane data integrity
• Data scrambling and disparity tracking to minimize baseline wander and maintain DC
balance
• Support for all Synchronization, Scrambler State, Diagnostic, and Skip Word Block Types
• Programmable Rate Limiting circuitry
• Segment-mode and Packet-mode transmission format
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