Achronix Speedster22i Interlaken - Manual (Page 14)

Figure 4: TX Clock Domains
hs_if per_lane_tx
tx_striping
clk tx_serdes_refclk
serDes
IIPC Core
hs_if per_lane_tx serDes
hs_if per_lane_tx serDes
hs_if per_lane_tx serDes
hs_if per_lane_tx serDes
hs_if per_lane_tx serDes
hs_if per_lane_tx serDes
hs_if per_lane_tx serDes
hs_if per_lane_tx serDes
hs_if per_lane_tx serDes
hs_if per_lane_tx serDes
hs_if per_lane_tx serDes
Interface to user logic in the FPGA Core
UG032, May 15, 2014 14