Cirrus Logic EP7311 - Manual (Page 5)

DS506F2
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Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 5
EP7311
High-Performance, Low-Power System on Chip
List of Figures
Figure 1. A Maximum EP7311 Based System ..............................................................................................................12
Figure 2. Legend for Timing Diagrams .........................................................................................................................15
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ............................................................................17
Figure 4. SDRAM Burst Read Cycle Timing Measurement ..........................................................................................18
Figure 5. SDRAM Burst Write Cycle Timing Measurement ..........................................................................................19
Figure 6. SDRAM Refresh Cycle Timing Measurement ................................................................................................20
Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22
Figure 8. Static Memory Single Write Cycle Timing Measurement ...............................................................................23
Figure 9. Static Memory Burst Read Cycle Timing Measurement ................................................................................24
Figure 10. Static Memory Burst Write Cycle Timing Measurement ..............................................................................25
Figure 11. SSI1 Interface Timing Measurement ...........................................................................................................26
Figure 12. SSI2 Interface Timing Measurement ...........................................................................................................27
Figure 13. LCD Controller Timing Measurement ..........................................................................................................28
Figure 14. JTAG Timing Measurement .........................................................................................................................29
Figure 15. 256-Ball PBGA Package ..............................................................................................................................30
List of Tables
Table A. Power Management Pin Assignments ..............................................................................................................6
Table B. Static Memory Interface Pin Assignments ........................................................................................................6
Table C. SDRAM Interface Pin Assignments ..................................................................................................................7
Table D. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7
Table E. MCP Interface Pin Assignments .......................................................................................................................7
Table F. CODEC Interface Pin Assignments ..................................................................................................................8
Table G. SSI2 Interface Pin Assignments .......................................................................................................................8
Table H. Serial Interface Pin Assignments .....................................................................................................................8
Table I. LCD Interface Pin Assignments .........................................................................................................................8
Table J. Keypad Interface Pin Assignments ...................................................................................................................9
Table K. Interrupt Controller Pin Assignments ................................................................................................................9
Table L. Real-Time Clock Pin Assignments ....................................................................................................................9
Table M. PLL and Clocking Pin Assignments .................................................................................................................9
Table N. DC-to-DC Converter Interface Pin Assignments ............................................................................................10
Table O. General Purpose Input/Output Pin Assignments ...........................................................................................10
Table P. Hardware Debug Interface Pin Assignments ..................................................................................................10
Table Q. LED Flasher Pin Assignments .......................................................................................................................10
Table R. MCP/SSI2/CODEC Pin Multiplexing ...............................................................................................................11
Table S. Pin Multiplexing ..............................................................................................................................................11
Table T. 256-Ball PBGA Ball Listing .............................................................................................................................32
Table U. JTAG Boundary Scan Signal Ordering ...........................................................................................................35
Table V. Acronyms and Abbreviations ..........................................................................................................................40
Table W. Unit of Measurement .....................................................................................................................................40
Table X. Pin Description Conventions ..........................................................................................................................41