Cirrus Logic EP7311 - Manual (Page 39)

DS506F2

Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 39
EP7311
High-Performance, Low-Power System on Chip
1) See EP7311 Users’ Manual for pin naming / functionality.
2) For each pad, the JTAG connection ordering is input,
output, then enable as applicable.
D6 nMWE/nSDWE O 358
B4 nMOE/nSDCAS O 360
E6 nCS[0] O 362
A3 nCS[1] O 364
D5 nCS[2] O 366
B3 nCS[3] O 368
A2 nCS[4] O 370
Table U. JTAG Boundary Scan Signal Ordering (Continued)
PBGA
Ball
Signal Type Position