Cirrus Logic EP7311 - Manual (Page 3)

DS506F2
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Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 3
EP7311
High-Performance, Low-Power System on Chip
Table of Contents
FEATURES .........................................................................................................................................................2
OVERVIEW ..................................................................................................................................................................2
Processor Core - ARM720T ..................................................................................................................................6
Power Management ..............................................................................................................................................6
MaverickKey™ Unique ID .....................................................................................................................................6
Memory Interfaces .................................................................................................................................................6
Digital Audio Capability .........................................................................................................................................7
Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................7
Multimedia Codec Port (MCP) ...............................................................................................................................7
CODEC Interface ..................................................................................................................................................8
SSI2 Interface ........................................................................................................................................................8
Synchronous Serial Interface ................................................................................................................................8
LCD Controller .......................................................................................................................................................8
Interrupt Controller ................................................................................................................................................9
Real-Time Clock ....................................................................................................................................................9
PLL and Clocking ..................................................................................................................................................9
DC-to-DC converter interface (PWM) ..................................................................................................................10
Timers .................................................................................................................................................................10
General Purpose Input/Output (GPIO) ................................................................................................................10
Hardware debug Interface ...................................................................................................................................10
Internal Boot ROM ...............................................................................................................................................10
Packaging ............................................................................................................................................................10
Pin Multiplexing ................................................................................................................................................... 11
System Design ....................................................................................................................................................12
ELECTRICAL SPECIFICATIONS ......................................................................................................13
Absolute Maximum Ratings .................................................................................................................................13
Recommended Operating Conditions .................................................................................................................13
DC Characteristics ..............................................................................................................................................13
Timings ...............................................................................................................................................15
Timing Diagram Conventions ....................................................................................................................15
Timing Conditions ......................................................................................................................................15
SDRAM Interface ................................................................................................................................................16
SDRAM Load Mode Register Cycle ..........................................................................................................17
SDRAM Burst Read Cycle .........................................................................................................................18
SDRAM Burst Write Cycle .........................................................................................................................19
SDRAM Refresh Cycle ..............................................................................................................................20
Static Memory ......................................................................................................................................................21
Static Memory Single Read Cycle .............................................................................................................22
Static Memory Single Write Cycle ..............................................................................................................23
Static Memory Burst Read Cycle ...............................................................................................................24
Static Memory Burst Write Cycle ...............................................................................................................25
SSI1 Interface ......................................................................................................................................................26
SSI2 Interface ......................................................................................................................................................27
LCD Interface ......................................................................................................................................................28
JTAG Interface ....................................................................................................................................................29
Packages ............................................................................................................................................30
256-Ball PBGA Package Characteristics ............................................................................................................30
256-Ball PBGA Package Specifications ....................................................................................................30
256-Ball PBGA Pinout (Top View) .............................................................................................................31
256-Ball PBGA Ball Listing ........................................................................................................................32
JTAG Boundary Scan Signal Ordering ................................................................................................................35