Cirrus Logic CS8406 User Manual

Cs8406, 192 khz digital audio interface transmitter, Features

Table of contents

Document Outline

1. Characteristics and Specifications
Specified Operating Conditions
Absolute Maximum Ratings
DC Electrical Characteristics
Digital Input Characteristics
Digital Interface Specifications
Transmitter Characteristics
Switching Characteristics
Switching Characteristics - Serial Audio Ports
- Figure 1. Audio Port Master Mode Timing
- Figure 2. Audio Port Slave Mode and Data Input Timing
Switching Characteristics - Control Port - SPI Mode
- Figure 3. SPI Mode Timing
Switching Characteristics - Control Port - I·C Mode
- Figure 4. I·C Mode Timing
2. Typical Connection Diagrams
- Figure 5. Recommended Connection Diagram for Software Mode
- Figure 6. Recommended Connection Diagram for Hardware Mode
3. General Description
- 3.1 AES3 and S/PDIF Standards Documents
4. Three-Wire Serial Input Audio Port
- Figure 7. Serial Audio Input Example Formats
5. AES3 Transmitter
- 5.1 TXN and TXP Drivers
- 5.2 Mono Mode Operation
- 5.3 Transmitted Frame and Channel Status Boundary Timing
  - Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data, Stereo Mode
  - Figure 9. AES3 Transmitter Timing for C, U, and V Pin Input Data, Mono Mode
6. Control Port Description
- 6.1 SPI Mode
  - Figure 10. Control Port Timing in SPI Mode
- 6.2 I·C Mode
  - Figure 11. Control Port Timing, I·C Slave Mode Write
  - Figure 12. Control Port Timing, I·C Slave Mode Read
7. Control Port Register Summary
- Table 1. Control Register Map Summary
8. Control Port Register Bit Definitions
- 8.1 Memory Address Pointer (MAP)
- 8.2 Default = ‘000000’Control 1 (01h)
- 8.3 Control 2 (02h)
- 8.4 Data Flow Control (03h)
- 8.5 Clock Source Control (04h)
- 8.6 Serial Audio Input Port Data Format (05h)
- 8.7 Interrupt 1 Status (07h) (Read Only)
- 8.8 Interrupt 2 Status (08h) (Read Only)
- 8.9 Interrupt 1 Mask (09h)
- 8.10 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh)
- 8.11 Interrupt 2 Mask (0Ch)
- 8.12 Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)
- 8.13 Channel Status Data Buffer Control (12h)
- 8.14 User Data Buffer Control (13h)
- 8.15 Channel Status Bit or User Bit Data Buffer (20h - 37h)
- 8.16 CS8406 I.D. and Version Register (7Fh) (Read Only)
9. Pin Description - Software Mode
10. Hardware Mode
- 10.1 Channel Status, User and Validity Data
  - Figure 13. Hardware Mode Data Flow
  - Table 2. Hardware Mode COPY/C and ORIG Pin Functions
- 10.2 Serial Audio Port
11. Pin Description - Hardware Mode
12. Applications
- 12.1 Reset, Power Down and Start-Up
- 12.2 ID Code and Revision Code
- 12.3 Power Supply, Grounding, and PCB layout
- 12.4 Synchronization of Multiple CS8406s
13. Package Dimensions
14. Ordering Information
15. Appendix A: External AES3/SPDIF/IEC60958 Transmitter Components
- 15.1 AES3 Transmitter External Components
- 15.2 Isolating Transformer Requirements
16. Appendix B: Channel Status and User Data Buffer Management
- 16.1 AES3 Channel Status(C) Bit Management
- 16.2 AES3 User (U) Bit Management
  - 16.2.1 Mode 1: Transmit All Zeros
  - 16.2.2 Mode 2: Block Mode
17. Revision History